The field of the invention is that of forming trench capacitors in integrated circuits, in particular in DRAM arrays.
Workers in the field of the fabrication of DRAM arrays constantly strive to reduce the amount of area occupied by a memory cell in order to keep up with the constant shrinkage of lithography dimensions.
A technique that has been developed extensively is the fabrication of the storage capacitor in a very deep trench (about 8 microns in current practice) that has been etched into the semiconductor substrate.
The capacitance of a trench capacitor is proportional to the area of the trench walls and therefore to the product of the trench depth and the transverse dimensions.
Shrinking the transverse dimensions is a requirement of reducing the cell area. Increasing the depth becomes extremely difficult, if not impossible, as the trench technology shrinks to 100 nm generation and beyond. Increasing the depth means increasing the process time and increasing process cost.
One known technique in the art is to set the dimensions of the upper portion of the DRAM cells to reflect the need for contacts and bitlines and meanwhile to expand the transverse dimensions of the capacitor itself in the lower portion of the area that, on the surface, is occupied by contacts and other elements of the cell. This lateral expansion is referred to as “bottle etching”, since the cross section of the cell resembles a bottle, with the lower portion being wider than the neck.
This process has been carried out to the limit when adjacent cells are in danger of making contact.
Thus, the art needs a method of forming a trench capacitor that maintains a given pitch, while increasing the area of the capacitor formed in the semiconductor substrate.